FIFO

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity fifo is
	port(
		data_in	: in std_logic_vector(7 downto 0);
		notWR		: in std_logic;
		notRD		: in std_logic;
		init		: in std_logic;
		clk		: in std_logic;
		data_out	: out std_logic_vector(7 downto 0);
		full		: out std_logic;
		empty		: out std_logic
	);
end fifo;
 
architecture Behavioral of fifo is
	constant size : integer := 16;
	type RAM is array (integer range<>) of std_logic_vector(7 downto 0);
	signal count : std_logic_vector(size downto 0) := (others => \'0\');
	signal mem	: RAM (0 to size-1);
 
begin
	process(clk,data_in,notWR,notRD,init)		
	begin
		if (init = \'1\') then
			count <= (others => \'0\');
			empty <= \'1\';
			full <= \'0\';
			data_out <= \"ZZZZZZZZ\";
		else
			if (notWR = \'0\' and rising_edge(clk) and count < size) then
				mem(conv_integer(count)) <= data_in;
				count <= count + \'1\';
			end if;
 
			--if (notRD = \'0\' and rising_edge(clk)) then
			if (falling_edge(notRD)) then
				if (count > 0) then
					data_out <= mem(0);
					for i in 0 to size-2 loop
						mem(i) <= mem(i+1);
					end loop;
					count <= count - \'1\';
				else
					data_out <= \"ZZZZZZZZ\";
				end if;
			end if;
			if (count = size) then
				full <= \'1\';
			else
				full <= \'0\';
			end if;
			if (count = 0) then
				empty <= \'1\';
			else
				empty <= \'0\';
			end if; 
		end if;
	end process;
end Behavioral;